Chalcogenide materials are an emerging class of commercial electronic materials that exhibit switching, memory, logic, and processing functionality. The basic principles of chalcogenide materials were developed by S. R. Ovshinsky in the 1960's and much effort by him and others around the world in the past few decades have led to advancements in the underlying science that governs the structure and properties of chalcogenide materials and an expansion of the range of practical application to which chalcogenide materials can be put.
Early work in chalcogenide devices demonstrated an electrical switching behavior in which switching from a resistive state to a conductive state was induced upon application of a voltage at or above a threshold voltage. Although the threshold voltage is formally a property of the device, the response of the active chalcogenide material to the voltage is the critical factor underlying the magnitude of the threshold voltage. The voltage-induced resistive-to-conductive transformation is the basis of the Ovonic Threshold Switch (OTS) and remains an important practical feature of chalcogenide materials. The OTS provides highly reproducible switching at ultrafast switching speeds for over 1013 cycles. Basic principles and operational features of the OTS are presented, for example, in U.S. Pat. Nos. 3,271,591; 5,543,737; 5,694,146; and 5,757,446; the disclosures of which are hereby incorporated by reference, as well as in several journal articles including “Reversible Electrical Switching Phenomena in Disordered Structures”, Physical Review Letters, vol. 21, p. 1450-1453 (1969) by S. R. Ovshinsky; “Amorphous Semiconductors for Switching, Memory, and Imaging Applications”, IEEE Transactions on Electron Devices, vol. ED-20, p. 91-105 (1973) by S. R. Ovshinsky and H. Fritzsche; the disclosures of which are hereby incorporated by reference.
Other important applications of chalcogenide materials include electrical and optical memory devices. One type of chalcogenide memory device utilizes the wide range of resistance values available for the material as the basis of memory operation. Each resistance value corresponds to a distinct structural state of the chalcogenide material and one or more of the states can be selected and used to define operational memory states. Chalcogenide materials exhibit a crystalline state or phase as well as an amorphous state or phase. Different structural states of a chalcogenide material differ with respect to the relative proportions of crystalline and amorphous phase in a given volume or region of chalcogenide material. The range of resistance values is bounded by a set state and a reset state of the chalcogenide material. The set state is a low resistance structural state whose electrical properties are primarily controlled by the crystalline portion of the chalcogenide material and the reset state is a high resistance structural state whose electrical properties are primarily controlled by the amorphous portion of the chalcogenide material.
Each memory state of a chalcogenide memory material corresponds to a distinct resistance value and each memory resistance value signifies unique informational content. Operationally, the chalcogenide material can be programmed into a particular memory state by providing an electric current pulse of appropriate amplitude and duration to transform the chalcogenide material into the structural state having the desired resistance. By controlling the amount of energy provided to a chalcogenide material, it is possible to control the relative proportions of crystalline and amorphous phase regions within a volume of the material and to thereby control the structural (and memory) state of the chalcogenide material.
Each memory state can be programmed by providing the current pulse characteristic of the state and each state can be identified or read in a non-destructive fashion by measuring the resistance. Programming among the different states is fully reversible and the memory devices can be written and read over a virtually unlimited number of cycles to provide robust and reliable operation. The variable resistance memory functionality of chalcogenide materials is currently being exploited in the OUM (Ovonic Universal (or Unified) Memory) devices that are beginning to appear on the market. Basic principles and operation of OUM type devices are presented, for example, in U.S. Pat. Nos. 6,859,390; 6,774,387; 6,687,153; and 6,314,014; the disclosures of which are incorporated by reference herein as well as in several journal articles including “Low Field Amorphous State Resistance and Threshold Voltage Drift in Chalcogenide Materials”, published in IEEE Transactions on Electron Devices, vol. 51, p. 714-719 (2004) by Pirovana et al.; and “Morphing Memory” published in IEEE Spectrum, vol. 167, p. 363-364 (2005) by Weiss.
The general behavior (including switching, memory, and accumulation) and chemical compositions of chalcogenide materials have been described, for example, in the following U.S. Pat. Nos. 6,671,710; 6,714,954; 6.087,674; 5,166,758; 5,296,716; 5,536,947; 5,596,522; 5,825,046; 5,687,112; 5,912,839; and 3,530,441, the disclosures of which are hereby incorporated by reference. These references also describe proposed mechanisms that govern the behavior of the chalcogenide materials, including the structural transformations from a crystalline state to an amorphous state (and vice versa) via a series of partially crystalline states that underlie much of the operational characteristics of electrical and optical chalcogenide materials.
Current commercial development of the chalcogenide materials and devices is also oriented toward the fabrication of arrays of devices. Chalcogenide materials offer the promise of high density memory, logic and neural arrays that can operate using either a traditional binary data storage protocol or a non-binary, multilevel protocol. Chalcogenide arrays further offer the prospect of integrating, on a single chip, both memory and processing functionality.
In order to further expand the commercial prospects of chalcogenide phase change memories, it is necessary to devise further improvements in the chemical and physical properties of chalcogenide materials as well as in manufacturing processes. A current issue in terms of the properties of chalcogenide materials is the need to improve the thermal stability of the materials. Data in a chalcogenide material are retained as a structural state of the material, so any tendency of the structural state to transform with temperature represents a potential undesirable mechanism of erasing or losing data. Many chalcogenide memory materials retain their structural states for long periods of time at room temperature, but become susceptible to variations in the structural state upon increasing temperature. In practical terms, this limits the temperature environment in which chalcogenide memory devices can be utilized as well as the temperatures that can be employed in processing or manufacturing. It is desirable to develop new chalcogenide compositions having structural states that are stable over an ever-increasing range of temperatures.
In most currently-envisioned memory applications, chalcogenide materials are operated in a binary mode where the memory states correspond to, or approximately correspond to, the set state and the reset state since these states provide the greatest contrast in resistance and thus facilitate discrimination of the state of the material during read out. In most of the fabrication processes contemplated for commercial production of chalcogenide memory devices, the chalcogenide material is deposited on a substrate; electrical contact layer or other layer. After deposition the chalcogenide material is in an amorphous or otherwise disordered state and is converted to a crystalline state during subsequent processing. In completed, fully fabricated devices, it is sometimes necessary to electrically exercise or “form” the chalcogenide material to ready the device for consistent operation as the active material of a memory element. The formation process includes the step of transforming the as-processed chalcogenide device to the optimum state for product use. In devices that employ the widely used Ge2Sb2Te5 alloy, the formation process requires multiple cycles of setting and resetting to achieve a set state resistance that stabilizes to a desirable and reproducible value.
In order to increase the efficiency of manufacturing, it is desirable to develop chalcogenide materials and device structures that can be electrically conditioned for practical operation in the minimum time. In U.S. patent application Ser. No. 11/200,466 (the '466 application), the instant inventors identified a series of new chalcogenide compositions that required little or no formation. The alloys include Ge and a column V element, where the column V element is preferably Sb. In some embodiments, the alloys further included Te. Relative to the widely-used Ge2Sb2Te5 composition, the alloys were lean in Ge and/or Te. The alloys of the '466 application may be referred to as “off-tieline” alloys because the compositions of the alloys are located away from the tieline connecting Sb2Te3 and GeTe on a ternary Ge—Sb—Te phase diagram.
In addition to less stringent post-processing formation requirements, it is further desirable to develop chalcogenide alloys that exhibit fast crystallization speeds over a series of memory states that extend over a wide dynamic range of resistance.